Part of the final year digital systems design module included a mini VHDL project. The aim of this project is to extend the knowledge learned in second year and incorporate it all into a single project.
In this mini-project, you are required to design, verify and implement of a digital phase shifter and frequency measurement circuit using a Xilinx FPGA. In the past a similar design has been used as a driver for a resonant frequency load-cell.
The operating principle of this system is to keep the load cell resonator oscillating at (or very close to) its resonant frequency. When a load is applied to the resonator load cell there is a change in the resonant frequency which is proportional to the load applied. By measuring the frequency it is possible to determine the load applied to the cell.
The circuit to be designed here is used to maintain the sensor in resonance over a (wide) frequency range while also measuring the frequency of oscillation. The input (SENSOR_IN) to the circuit is a digital square wave (0 – 3.3V) of varying frequency output from the resonator which must be used (by the FPGA) to generate a 90o phase-shifted version of the signal which is then used to drive the resonator and keep it oscillating. The FPGA also needs to use the output from the load-cell resonator to measure its oscillating frequency of the resonator. The input signal frequency must be calculated by taking samples over a period of time.
VHDL Mini Project Report
Most of the project development has taken place at home. I did not have an oscilloscope to check the output waveform for debugging, hence esp8266 SoC was configured using interrupts to calculate the angle between input and output single. @see repo for more info.